Embodiments of the present disclosure may generally relate to a data inversion circuit, and more particularly to a data bus inversion circuit that is smaller in size while reducing power consumption.
A semiconductor integrated circuit (IC) may include a semiconductor memory device that stores data therein in response to a control signal from a Central Processing Unit (CPU) or a Graphics Processing Unit (GPU). One of the factors that may affect performance of the semiconductor IC such as a main memory or a graphic memory is a data processing speed.
Examples of various technologies that can reduce power consumption of the semiconductor IC may include a data bus inversion circuit. For example, when a controller during a write operation or a semiconductor memory device during a read operation is sending out data, if the number of bits having “0” (logic low value) in a data byte is five or more, then the data bus inversion circuit inverts the entire byte. By contrast, if at least five bits in a data byte are “1” (logic high value), then the data bus inversion circuit does not invert the data byte.
The semiconductor memory device receives data through a data bus during a write operation and transmits the data over global input/output (I/O) lines. However, if the total number of signals transitioning at the global I/O lines by the data bus inversion circuit increases, an unnecessary toggle current may be generated. Therefore, in sending data by using the data bus inversion circuit, it is importance to minimize the total number of signals transitioning to reduce a toggle current of a transmit (Tx) channel.